AMD flips the bird at Intel as it glides past in CPU-GPU stakes
AMD is talking up internal engineering advances as it looks forward to the introduction of its first hybrid CPU-GPU datacenter chip and more Epyc products, just as rival Intel confirms delays to its own GPU lineup.
Speaking at the Morgan Stanley Technology, Media and Telecom conference, AMD CTO Mark Papermaster pointed to the progress the company is making with the Instinct MI250 accelerator and its successor, the MI300.
Papermaster said AMD had started development of the Instinct GPUs when the company saw “where AI was heading,” and this could be accelerated by parallel and vector processing.
“We focused first on HPC because we had a very good software stack already to build on. It’s called the ROCm stack. And so ROCm 4.0 was released a couple of years ago that was production level for HPC. And having this type of leading-edge hardware and a production HPC stack led to key wins across the HPC sector,” he claimed.
ROCm 5.0 added support for PyTorch, TensorFlow and other machine learning frameworks, and is now production level for AI processing, he said.
“If you go to PyTorch, you see only two software stacks rated at production level on Linux, and that is AMD and our GPU competitor Nvidia,” Papermaster claimed.
The MI250 has been available for about a year now and AMD has talked about the next-generation chip, the MI300, since about last June, so what is happening with that?
“We’ll be announcing that second half of this year, and ramping in 2024,” Papermaster stated, describing the company’s hybrid CPU-GPU chip as “a beast.” That’s because “it takes four GPU CPUs – four Genoa CPUs – and embeds it with our graphics processing,” he explained.
That means CPU cores based on the 4th Gen Epyc architecture combined with a GPU based on the next-gen CDNA 3 architecture, as detailed previously.
Papermaster compared this to AMD’s earlier accelerated processing unit (APU) chips for client devices, which combined CPUs and consumer GPU functions gained from its acquisition of ATI.
“Just like we shipped combined CPU and GPU for years in PC and embedded markets, we’ve now brought that approach to the datacenter with the Instinct 300,” he said, adding that AMD is primarily targeting hyperscalers, rather than trying to hit every single vertical market with its accelerator products.
The MI300 was to have faced a new GPU product from rival Intel, Rialto Bridge, which was due to start sampling to vendors in the middle of this year. However, this has now been canned, as Intel disclosed last week, and Falcon Shores, Intel’s own CPU-GPU chip with x86 CPU cores and Xe GPU cores, is now delayed until 2025.
Papermaster also briefly mentioned Siena, another upcoming member of AMD’s 4th Gen Epyc server processor family that will target edge computing and telecoms use cases.
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Siena will be “a telco optimized version of our fourth-generation Epyc coming out second half of this year,” he said, and talked up the synergy he saw between this and the telecoms portfolio AMD gained from its purchase of Xilinx, which the company had on show at the recent Mobile World Congress event in Barcelona.
“With the advent of 5G, AMD now has an end-to-end from the control plane with the presence we already had with our Epyc product line,” Papermaster said.
Siena is expected to have up to 64 Zen 4 cores and will be optimized for performance-per-watt, but otherwise it isn’t clear what features it will have to make it better suited for telecoms applications. Intel’s Xeon D family has built-in networking and quality of service (QoS) functions, for example.
Papermaster was also asked about Inspur, the China-based OEM that was recently added to the entity list of restricted vendors by the US Department of Commerce. Inspur supplies servers to many cloud providers and HPC customers, and has links with many of the big US tech companies.
“Like everyone in our industry, we of course follow all of the guidelines of export controls from the US government, including the Entity List,” he said. “We’re seeking clarification as I think the rest of the industry is, because Inspur is a large holding company. It serves many markets. So, we’re looking to get clarification on those guidelines.”
Papermaster also spoke about Moore’s Law, as he has done at previous events, and said that processor companies had to adapt to the slowing of improvements in transistor density.
“Process technology is foundational in our semiconductor industry,” he said, “but Moore’s Law, it’s slowing down. The cost of transistors is going up per node. The type of scaling you get, the type of circuitry that gets the benefit out of each new technology node is getting less. Some of the circuit types don’t scale.”
This means that a chip design and the process technology really have to be developed closely together more than ever before, according to Papermaster, and this is what led AMD to a modular approach such as the Infinity architecture, which allows the partitioning out of different circuit types to different process nodes.
“That said, the new nodes remain vitally important,” he explained. “Those transistors want to operate at the most efficiency you can. And that’s what each technology new node brings. The transistors and the new nodes are getting more expensive, but they’re still giving you efficiency gains, more performance at less watts of energy expended.” ®